1. Field
Embodiments of this invention relate to a semiconductor memory device and, more particularly, to a semiconductor memory device having a parallel bit test circuit and an associated method.
2. Related Art
A semiconductor memory device performs a parallel bit test responsive to a test mode setting command. The semiconductor memory device then writes test pattern data from a tester to a memory cell array responsive to a write command. Afterwards, the semiconductor memory device reads data from the memory cell array, compares the two data read from the memory cell array, and outputs a compared result. For example, the semiconductor memory device writes a logic ‘1’ into a first pair of memory cells, a logic ‘0’ into second pair of the memory cells, a logic ‘0’ into a third pair of the memory cells and a logic ‘1’ into a forth pair of the memory cells. The semiconductor memory device then reads eight memory cells and compares two data from each of four pairs of memory cells. The semiconductor memory device generates a ‘pass’ test result when the two data from each of four pairs of memory cells are logically identical. The semiconductor memory device generates a ‘fail’ test result when two data from any pair of the four pairs of the memory cells are not logically identical.
FIG. 1 is a circuit diagram of a parallel bit test circuit in a semiconductor memory device. Referring to FIG. 1, three comparing circuits 110, 120 and 130 compare data, e.g., eight data bits, from eight memory cells. The parallel bit test circuit outputs the result of the comparison through a pin OUT. The first comparing circuit 110 may have four comparators, e.g., exclusive-OR (XOR) gates. The second comparing circuit 120 may have two comparators, e.g., OR gates. The third comparing circuit 130 may have a comparator, e.g., an OR gate.
The parallel bit test circuit illustrated in FIG. 1 outputs a logic ‘1’ when two data read operations from any of the four pairs of the memory cells are not logically identical.
FIG. 2A is a conceptual diagram illustrating a disadvantage associated with the parallel bit test circuit of FIG. 1. FIG. 2A illustrates the case that logic ‘1’s are written in eight memory cells and data are read from the eight memory cells. Referring to FIG. 2A, when the data from the memory cell DIO0_E is read incorrectly, the first comparing circuit outputs are not all logic ‘0’s and the result of the parallel bit test is a logic ‘1’. The logic ‘1’ of the parallel bit test result means the memory cells failed. The tester cannot identify which memory cell of the eight memory cells tested is the failed memory cell. And the tester cannot quantify how many memory cells failed. FIG. 2B is a conceptual diagram illustrating a disadvantage associated with the parallel bit test circuit of FIG. 1. FIG. 2B illustrates the case where “0111” patterns are written into eight cells and data are read from the eight memory cells. Referring to FIG. 2B, when data from the memory cell DIO0_E is read incorrectly, the first comparing circuit outputs a logic ‘0’ as a result of comparing two data from two cells DIO0_E and DIO2_E. The result of comparing two data from two cells DIO0_E and DIO2_E cancel out because of the third comparing circuit. The tester receiving the result of the parallel bit test will not detect the defective or failed memory cell.
As shown in FIGS. 1, 2A, and 2B, the parallel bit test circuit is incapable of using various test patterns. For example, the conventional parallel bit test circuit cannot use the “0111” pattern. And the parallel bit test circuit cannot identify which memory cell fails and how many memory cells fail.